The present invention relates to an I2L delay circuit and a ring oscillator incorporating the same.
FIG. 17 shows a delay circuit arranged in a conventionally known manner. In FIG. 17, reference numeral 1701 denotes a first I2L inverter, 1702 a second I2L inverter, and 1703 a capacitor. The delay introduced by the delay circuit of FIG. 17 is a time taken for the input terminal voltage of the I2L inverter 1702 (the voltage across the capacitor 1703) to grow to the threshold voltage of the I2L inverter 1702 as the capacitor 1703 coupled to the input of the I2L inverter 1702 is charged by the input terminal current of the I2L inverter 1702. The input terminal current of the I2L inverter 1702 is the collector current of a laterally structured p-n-p I2L transistor constituting the I2L inverter 1702 and is an injection current of the I2L inverter 1702.
Japanese Laid-Open Patent Application No. 9-172356/1997 (Tokukaihei 9-172356; published on Jun. 30, 1997) discloses a delay circuit capable of introducing variable delays. The delay circuit, including a plurality of inverting buffers and switches as shown in FIG. 18, alters the delay through the control of the switches.
In FIG. 18, reference numeral 1804 denotes a first inverting buffer, 1801a a second inverting buffer, 1801b a third inverting buffer, 1801c a fourth inverting buffer, 1801d a fifth inverting buffer, 1802a a first switch, 1802b a second switch, 1802c a third switch, 1802d a fourth switch, and 1803 a capacitor. At least one of the first to fourth switches 1802a-1802d is closed at any given time.
A distinction of the delay circuit in FIG. 18 lies in that the number of inverting buffers (other than the first inverting buffer 1804 and the second inverting buffer 1801a) involved in charging/discharging of the capacitor 1803 is changed through the opening/closing of the second to fourth switches 1802b-1802d connected in series with the respective third to fifth inverting buffers 1801b-1801d to produce delays of various values.
Specifically, in the delay circuit of FIG. 18, the more the connected inverting buffers, the greater the current for charging/discharging the capacitor 1803. Therefore, the delay can be varied by altering the number of the inverting buffers.
The foregoing prior art has following problems.
In the delay circuit of FIG. 17, if the capacitor 1703 is integrated in an integrated circuit (not shown), the capacitance (electrostatic capacitance) of the capacitor 1703, and hence the delay, become invariable. By contrast, if the capacitor 1703 is provided external to the integrated circuit, the delay is variable by changing the capacitance of the capacitor 1703; nevertheless, the need arises to dispose the capacitor 1703 externally to the integrated circuit and to equip the integrated circuit with a terminal at which the integrated circuit is coupled to the capacitor 1703. These requirements cause serious problems in mounting of the integrated circuit.
In the delay circuit of FIG. 18, the second to fifth inverting buffers 1801a-1801d involved in charging/discharging of the capacitor 1803 need be arranged to include a current supply (not shown) and require an equal number of switches (2a-2d), which renders the actual circuit configuration complex.
In addition, to obtain a substantially long delay, either the capacitance of the capacitor 1803 must be sufficiently large or the charge current of the capacitor 1803 must be sufficiently small. Integration of a large capacitance capacitor 1803 in an integrated circuit, however, gives rise to a problem of too large a chip area.
Further referring to the delay circuit of FIG. 18, since the charge current of the capacitor 1803 is alterable by changing the number of inverting buffers used, each energized inverting buffer conducts a minimum current to charge the capacitor 1803; for these reasons, it is difficult to reduce the charge current of the capacitor 1803 to a sufficiently low value. Even if the charge current is successfully decreased to a sufficiently low value, noise could cause the output from the delay circuit to fluctuate (change).
The present invention addresses the foregoing problems and has an object to present a delay circuit of simple configuration that accounts for a small area in an integrated circuit and that is capable of introducing any given delay and also to present a ring oscillator incorporating the delay circuit.
A delay circuit in accordance with the present invention, in order to achieve the above object, includes: a first I2L inverter and a second I2L inverter connected in cascade with each other; and a capacitor interposed between a ground and a connecting point of the first and second inverters and is characterized by the following features.
The delay circuit is characterized in that it includes at least one third I2L inverter with a plurality of output terminals at least one of which is connected to an input terminal of the third I2L inverter and that the third I2L inverter is connected to adjust a charge current of the capacitor.
In the foregoing invention, the delay refers to the time taken for the terminal voltage of the capacitor to reach the threshold voltage of the second I2L inverter as a result of the capacitor being charged by the current from the input of the second I2L inverter and is determined by the electrostatic capacitance of the capacitor.
However, a typical capacitor has a fixed electrostatic capacitance, and therefore the delay is invariable. By contrast, if the capacitor is provided external to the integrated circuit, the delay becomes variable by changing the electrostatic capacitance of the capacitor; nevertheless, the need arises to dispose the capacitor external to the integrated circuit and to equip the integrated circuit with a terminal at which the integrated circuit is coupled to the capacitor. These requirements pose serious problems in mounting of the integrated circuit.
To address this dilemma, the delay circuit includes at least one third I2L inverter connected to adjust a charge current of the capacitor. The provision of at least one third I2L inverter having an identical structure to that of the first and second I2L inverters enables adjustment of the charge current of the capacitor. The delay is therefore variable even if the capacitor has a fixed electrostatic capacitance. Further, the capacitor need not have a large electrostatic capacitance and therefore accounts for a reduced area in an integrated circuit; further integration of the integrated circuit is thus achieved.
The more the third I2L inverters, the more the electrostatic capacitance of the capacitor can be reduced.
It is preferable that the third I2L inverter is switchable by a control signal as to whether or not the third I2L inverter will contribute to adjustment of the charge current of the capacitor.
When this is the case, the third I2L inverter is switchable by the control signal as to whether or not the third I2L inverter will contribute to adjustment of the charge current of the capacitor. With two or more third I2L inverters provided, the amount by which the charge current of the capacitor is adjusted is variable through the control of the control signals. More precise delays therefore become available over a wider range.
It is preferable that the control signals are supplied to the third I2L inverters via an associated control signal input terminal of the third I2L inverters. When this is the case, external delay switching control becomes possible. In other words, the switching as to whether or not the third I2L inverter will contribute adjustment of the charge current of the capacitor is controllable by the control signal supplied to the third I2L inverters via the respective control signal input terminals. With two or more third I2L inverters provided, the charge current of the capacitor can be more precisely varied assuming a variety of values over a wider range through combinations of the control signals.
Incidentally, the charge current of the capacitor can be reduced by increasing the current passing through the third I2L inverter. By doing so, desirable large delays become available using a capacitor with a low electrostatic capacitance. This method, however, is not free from possible inconvenience: a reduced charge current may cause the output from the second I2L inverter to fluctuate: the voltage across the increasingly charged capacitor, when growing to the input threshold voltage of the second I2L inverter at which the output from the second I2L inverter inverts from the HIGH level to the LOW level, could be susceptible to noise and fluctuate around the input threshold voltage of the second I2L inverter.
To address this inconvenience, it is preferable that the control signal is supplied to the third I2L inverter via the second I2L inverter and causes the third I2L inverter to not contribute to adjustment of the charge current of the capacitor. When this is the case, the control signal supplied from the second I2L inverter causes the third I2L inverter to not contribute to adjustment of the charge current of the capacitor. As a result, since no adjustment in the charge current exists, once the voltage across the capacitor reaches the input threshold voltage of the second I2L inverter, the voltage across the capacitor is maintained stably.
Therefore, the voltage across the capacitor no longer fluctuates around the input threshold voltage of the second I2L inverter. The delay circuit is hence stable and supplies a steady output from t he second I2L inverter. Further, the configuration is so simple that mere line connection is added to feed the control signal as above and requires no additional gate or similar element; integration is therefore not degraded, and the delay circuit ensures a stable output.
It is preferable that the third I2L inverter includes: a transistor conducting a reference current; and a plurality of I2L transistors at least one of which is connected to the connecting point, with the remaining I2L transistors connect ed between the output terminal and the input terminal, and the plurality of I2L transistors conduct equal amounts of current having a value of the reference current divided by the number of the remaining I2L transistors.
When this is the case, if the remaining I2L transistors conduct no current, the charge current of the capacitor is not adjusted. By contrast, if the remaining I2L transistors conduct current (the reference current divided by the number of the remaining I2L transistors), an equal current is supplied to the at least one of I2L transistors via the connecting point. The charge current of the capacitor is thus adjusted. The plurality of I2L transistors, since configured to form a kind of current mirror, facilitate integration.
It is preferable that the third I2L inverter includes: a transistor conducting a reference current; and a plurality of I2L transistors at least one of which is connected to the connecting point, with the remaining I2L transistors between the output terminal and the input terminal; the plurality of I2L transistors conduct equal amounts of current having a value of the reference current divided by the number of the remaining I2L transistors; and the control signals are applied to bases of the plurality of I2L transistors so that the third I2L inverter conducts current when the I2L transistor is on and conducts no current when the I2L transistors are off.
When this is the case, the control signals are applied to bases of the plurality of I2L transistors. Consequently, when the I2L transistors are off, the third I2L inverter conducts no current, and the charge current of the capacitor is not adjusted. By contrast, when the I2L transistor is on, all the I2L transistors conduct equal amounts of current (the reference current divided by the number of the remaining I2L transistors), and the charge current of the capacitor is adjusted. The plurality of I2L transistors, since configured to form a kind of current mirror, facilitate integration.
It is preferable that the second I2L inverter is realized by a plurality of the second I2L inverters connected in parallel. When this is the case, the current flowing from the second I2L inverters to the capacitor increases according to the number of the second I2L inverters connected in parallel, and the current adjust range of the capacitor is expanded accordingly. Thus, the delay circuit can produce delays of various values covering a wide range without excessively reducing the charge current of the capacitor.
It is preferable that a ring oscillator incorporates any one of forgoing delay circuits wherein: an odd number of I2L inverters are connected in cascade to an output of the delay circuit; and the output of the cascade connection is connected to an input of the first I2L inverter. When this is the case, the ring oscillator oscillates at oscillation frequencies in accordance with the delays produced by the delay circuit. Thus, a ring oscillator can be provided which highly precisely varies the oscillation frequency over a wide range and which has a simple circuit structure accounting for a small area in an integrated circuit and thus achieving high integration.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.